Introduction of strained silicon has been essential for extending progress in transistor performance, especially for the p-type MOSFETs –. Certain strain patterns are known to more than triple hole mobility and double on-state current of p-type transistor , .
In addition to silicon strain engineering, there is an ongoing search for alternative channel materials to further speed up the MOSFETs –. The main objective of the search is to identify materials that have electrons and holes with low effective mass
However, there are limits to how far the effective mass should be lowered. There are several downsides to having carriers with low effective mass due to the broader wave function
The wider wave function means that the carrier has a broader spread in space and has higher probability of getting into undesired locations. For example, it leads to excessive gate leakage for the gate dielectrics with physical thickness below 2 nm. This was the reason behind scaling stagnation for conventional Si ON gate dielectric that was eventually solved by introducing High-K Metal Gate (HKMG) that is thick physically but thin electrically . Another example is Band-To-Band Tunneling (BTBT) that happens at the drain junction and increases the off-state leakage whenever the carrier wave function spans across the drain junction under high drain bias. MOSFETs with non-Si channels exhibit higher BTBT levels than Si MOSFETs –. Yet another example is direct Source-To-Drain Tunneling (STDT), which becomes noticeable for channel materials with high mobility at longer channel lengths than for Si –.
There are several different classes of materials of interest with very different desirable properties. For example, material for the transistor's channel has to satisfy the following criteria:
Provide high carrier mobility
Provide consistent behavior from one transistor to the next, with small random variability
Provide large enough bandgap to prevent band-to-band tunneling off-state leakage
Provide small enough bandgap with high Density Of States (DOS) to ensure large number of carriers in the channel for the on-state biasing conditions
Provide low enough effective carrier mass to ensure high on-state current
Provide high enough effective carrier mass to ensure low off-state current due to the direct source-to-drain tunneling
Provide crystal lattice size that is compatible with the adjacent materials and enables stress engmeermg
Provide high enough mechanical strength to prevent dislocations and cracking
Provide low enough mechanical strength to enable straining the channel by the adjacent materials for stress engmeermg
Provide the ability to introduce dopants to control the conductivity and threshold voltage
The dopants need to have shallow enough energy levels in the bandgap to prevent incomplete ionization at low temperatures
Provide low enough defect density to avoid excessive carrier recombination that degrades the transistor performance
Provide high enough defect density to quickly remove unintentional carriers generated by radiation (i.e. Single Event Upset (SEU)) or crosstalk with the adjacent transistors or Electro-Static Discharge (ESD)
Provide low enough density of dangling bonds at the interface with the gate dielectric to reduce carrier scattering and carrier trapping that degrade transistor performance
Provide sufficient bonding strength to the gate dielectric to prevent delamination
Provide consistent layer/film/wire size from one transistor to the next to ensure reproducible transistor behavior
Provide low enough interface roughness with the gate dielectric to reduce carrier surface scattering in narrow layers/films/wires and therefore high conductance
Provide workfunction that is compatible with the other key materials in the transistor: high enough barrier to the gate dielectric, within the range of gate workfunction to set required threshold voltages, and low enough barrier to the source and drain materials
Provide breakdown voltage that is at least 20% higher than the highest power supply voltage on the chip, which is usually 2.5 V for the input/output circuit
Cost effective material mining
Cost effective material synthesis/deposition
Available in sufficient quantities
Not toxic and environment friendly
Stable mechanically and chemically within the required temperature range and ambient conditions to prevent degradation of transistor behavior over time
Provide the ability to be etched with acceptable chemistry and timeframe for patterning blanket films into transistors
Provide the ability to be selectively grown/deposited on top of the patterned wafer
Provide the thermal stability that is compatible with the other materials on the same wafer, including channel materials for the n - type and p-type transistors in the Front End Of Line process (FEOL), and including the interconnects in the Back End Of Line process (BEOL)
Provide comparable performance to the other type of transistor on the same chip (i.e. the performances of n-type and p-type transistors have to be comparable for efficient circuit design)
Provide thermal properties that enable sufficient removal of the Joule heat generated during transistor operation
Beat silicon and other competing candidates in terms of on-state performance, off-state leakage, scalability for the target technology nodes, manufacturing yield, reliability during the target transistor lifetime and environment conditions, material cost, and manufacturing cost
This incomplete list illustrates how difficult it is to find new materials, yet finding it gives a tremendous advantage in the marketplace with a potential to dominate it.
In this work, we investigate behavior of short channel MOSFET transistors scaled in the range from 14nm through 2nm design rules. Besides nominal transistor performance, we also look at variability due to fin width fluctuations that are caused by a variety of process steps involved in fin patterning.
Key design rules for transistors scaling from 14nm technology node down to 2nm technology node are listed in table 1. The 14nm design rules correspond to FinFETs that are currently in production. We assume that FinFETs can be scaled down to at least 7nm design rules.
Starting at 5nm design rules, we evaluate nanowires as a possible FinFET replacement, because nanowires exhibit considerably better short channel behavior.
Power supply voltage is 0.7 V for the FinFETs, and 0.5 V for the nanowires. The off-state current is
In terms of channel materials, we assume that FinFETs have silicon channels, whereas for the nanowires we explore materials with effective masses ranging from 0.04 to 0.54. Typical FinFET and nanowire transistors are illustrated on Fig. 1.
Typical 3D geometries of a half of finfet (left) and a nanowire transistor (right). Nanowire transistor is shown with an enlarged scale for clarity. If scaled proportionally, a nanowire transistor with 5nm design rules would fit inside a diamond-shape epitaxial drain of a finfet with 14nm design rules.
We perform analysis of n-type MOSFETs only, using 3D NEGF tool QTX , . It is necessary to model quantum transport effects for nanowire transistors with short channel lengths listed in Table 1. The drift-diffusion electron transport model can be calibrated to the more advanced Boltzmann transport or NEGF models to reproduce quantum transport effects . In this project we used calibrated drift-diffusion model with ballistic mobility for the FinFETs and QTX for the nanowire transistor analysis.
Let's vary band structure properties without being restricted to specific existing materials to see what kind of band structure would work the best for particular design rules. Once we know what works the best, we can see which existing materials can be employed to get desirable band structure properties.
Figure 2 depicts on-state current normalized to
Nanowire transistor performance for different design rules and fixed off-state current of
For each point on Fig. 2 we adjust metal gate workfunction such that the
Each curve on Fig. 2 exhibits a peak performance, a relatively gentle performance degradation towards heavier electron mass, and a steep performance collapse towards lighter electron mass. The right part of the curve for 5nm design rules exhibits performance gain of about 15% when effective mass is reduced in half from 0.2, which is typical for relaxed Si. Such reduction of effective mass can be done by stress engineering and has been successfully used in the industry since 90nm node . The 5nm technology node might be the last one to have noticeable performance boost due to stress engineering.
The Ion vs m* curve for 4nm design rules exhibits a diminishing performance gain, and at 3nm design rules the electron mass needs to be increased from its stress-free value of 0.2 to 0.25 to catch the performance wave. This can be achieved by either using stress to slow down the electrons or by using alternative channel crystal directions that have higher electron mass in stress-free lattice. This would be a sharp departure from thinking of lighter effective masses and associated with them higher mobilities as an advantage.
The main reason behind performance collapse for channel materials with lighter electron masses, illustrated by steep current degradation for the left sides of all curves on Fig. 2 is the direct source-to-drain tunneling –.
Another way of plotting the data from Fig. 2 is represented on Fig. 3, with peak performance shown as a bright color, transitioning towards low performance through a series of increasingly darker colors.
Performance trade-off for channel materials with different effective masses as a function of nanowire transistor scaling. Effective mass values are shown for several si crystal orientations and for bulk ingaas.
It can be seen on Fig. 3 that silicon transistors are scaling gracefully at least down to 2nm design rules if appropriate crystal orientations are chosen. Alternatively, stress engineering can be employed to slow down electrons by ~2x towards 2nm design rules.
Another prominent feature displayed on Fig. 3 is the evidence that high mobility materials like InGaAs are at a severe disadvantage to silicon at 5nm design rules and beyond. Considering that III-V technology is not ready for 10nm node and that it is incompatible with 5nm design rules, the only opportunity window for it would be at 7nm node. Historically, the industry prefers technologies that can span several generations over a one-node-pony.
It has been observed that FinFETs are less sensitive to random dopant fluctuations  and as the FinFET shrinking progresses, they become increasingly sensitive to geometry fluctuations . Here, we explore the two key geometry variability mechanisms - the channel length and the fin width. Both the channel length and the fin width are currently patterned using spacer patterning technique, or SADP (Self-Aligned Double Patterning) . This technique is very effective at enforcing consistent patterning dimensions, but it is not perfect. Therefore, we evaluate how patterning imperfections impact transistor performance.
In this case, we keep the metal gate workfunction fixed, because we are interested in the impact of geometry fluctuations across the chip, where gate workfunction is designed to be uniform. As mentioned earlier, we use calibrated drift-diffusion approach with ballistic mobility model for the finFETs and NEGF model for the nanowire transistors. Figure 4 illustrates transistor sensitivity to channel length variations.
N-MOSFET's on-state current variation in response to channel length fluctuations. For reference is shown a one-sigma ion variation budget typical for the 14nm technology node.
It is interesting to observe increased FinFET sensitivity to channel length fluctuations as the scaling progresses, but then a sharp reduction of that sensitivity when we switch to nanowire transistor architecture at 5nm design rules. This is explained by the short channel effects creeping up with each subsequent FinFET generation, as the fin width scaling can not quite follow the required channel length scaling (see design rules in Table 1). However, a better electrostatics and therefore better short-channel effect immunity enables nanowire transistors to drastically suppress this variability mechanism.
On the contrary, transistor sensitivity to fin width fluctuations keeps increasing with scaling, and further accelerates with transition from FinFET to nanowire transistor architecture (Fig. 5).
N-MOSFET's sensitivity to fin width fluctuations. For the nanowire transistors, nanowire height is fixed, but the nanowire width varies, as it is determined by the fin width.
Two distinct curve slopes are observed on Fig. 5: One, less steep, for the FinFETs, and another, steeper, for the nanowire transistors. If the patterning fidelity is maintained near its present values of ~0.5 nm 3*sigma, it would triple fin width induced variability for 7nm FinFETs, and become more than ten-fold for nanowire transistors with 3nm design rules. This sensitivity trend dictates tolerance spec for transistor patterning as the scaling continues.
We applied advanced electron transport modeling to transistors scaling from FinFETs with 14nm design rules down to nanowire transistors with 2nm design rules. We found that silicon N-MOSFETs scale gracefully down to at least 2nm design rules. To achieve such scaling, the electrons will need to be slowed down with respect to standard Si, either by choosing alternative crystal orientations, or by applying stress engineering to slow down the electrons. One important observation is that high mobility materials like InGaAs are incompatible with scaling and can not be used at 5nm design rules and beyond. In terms of transistor sensitivity to geometry fluctuations, we found that FinFETs become increasingly sensitive to channel length variations with scaling, whereas nanowire transistors exhibit high tolerance to channel length fluctuations due to their superior resistance to short channel effects. A different story unfolds for N-MOSFET sensitivity to the fin width variations. Specifically, each subsequent FinFET generation exhibits ~70% higher fin width sensitivity, and transition to nanowire transistors accelerates it further to~100% per generation if fm width patterning fidelity remains unchanged. A four-fold improvement in patterning fidelity for 2nm technology node that would keep nanowire width variability within ~0.1nm can maintain current level of transistor sensitivity to fin width patterning imperfections.