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Summary | 8 Annotations
With an register on the left hand side of the expression, the assignment is executed on a positive clock edge if the condition is true. This is similar to how Verilog uses always @ (posedge clk) to specify synchronous logic.
2018/12/24 12:40
As long as the value is not assigned to be a register type (explained later), this tells the Chisel compiler to treat the value as wire.
2018/12/24 12:45
Unlike Verilog, specifying a register in Chisel tells the compiler to actually generate a positive edge triggered register
2018/12/24 12:46
val y = io.x val z = RegNext(y)
2018/12/24 12:55
input reset
2018/12/24 13:04
when (io.enable)
2018/12/24 13:05
To do this we need to provide our register declarations a little more information using the init parameter, or using the specialized constructor RegInit, with what value we want on a synchronous reset:
2018/12/24 13:08
// Register reset to zero val r0 = RegInit(0.U(1.W))
2018/12/24 13:17