icon-cookie
The website uses cookies to optimize your user experience. Using this website grants us the permission to collect certain information essential to the provision of our services to you, but you may change the cookie settings within your browser any time you wish. Learn more
I agree
Summary | 12 Annotations
n value sine lookup table using a ROM initialized
2018/12/24 08:20
most SRAMs in modern technologies (FPGA, ASIC) tend to no longer support combinational (asynchronous) reads
2018/12/24 08:22
Ports into Mems are created by applying a UInt index
2018/12/24 08:23
1024
2018/12/24 08:23
one write port
2018/12/24 08:23
sequential/synchronous read port
2018/12/24 08:23
// Create one write port and one read port.
2018/12/24 08:26
mem.write(addr, dataIn)
2018/12/24 08:27
dataOut := mem.read(addr, enable)
2018/12/24 08:27
Chisel will infer masks if the data type of the memory is a vector
2018/12/24 08:27
mask
2018/12/24 08:28
val mask = Wire(Vec(4, Bool()))
2018/12/24 08:29